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1 ?2008 integrated device technology, inc. october 2008 dsc 2740/13 idt7024s/l high-speed 4k x 16 dual-port static ram idt7024 easily expands data bus width to 32 bits or more using the master/slave select when cascading more than one device m/ s = h for busy output flag on master m/ s = l for busy input on slave interrupt flag on-chip port arbitration logic full on-chip hardware support of semaphore signaling between ports fully asynchronous operation from either port battery backup operation?2v data retention ttl-compatible, single 5v (10%) power supply available in 84-pin pga, flatpack, plcc, and 100-pin thin quad flatpack industrial temperature range (?40c to +85c) is available for selected speeds green parts availble, see ordering information functional block diagram features true dual-ported memory cells which allow simultaneous reads of the same memory location high-speed access ? military: 20/25/35/55/70ns (max.) ? industrial: 55ns (max.) ? commercial: 15/17/20/25/35/55ns (max.) low-power operation ? idt7024s active: 750mw (typ.) standby: 5mw (typ.) ? idt7024l active: 750mw (typ.) standby: 1mw (typ.) separate upper-byte and lower-byte control for multiplexed bus compatibility i/o control address decoder memory array arbitration interrupt semaphore logic address decoder i/o control r/ w l busy l a 11l a 0l 2740 drw 01 ub l lb l ce l oe l i/o 8l -i/o 15l i/o 0l -i/o 7l ce l oe l r/ w l sem l int l m/ s r/ w r busy r ub r lb r ce r oe r i/o 8r -i/o 15r i/o 0r -i/o 7r a 11r a 0r r/ w r sem r int r ce r oe r (2) (1,2) (1,2) (2) 12 12 notes: 1. (master): busy is output; (slave): busy is input. 2. busy outputs and int outputs are non-tri-stated push-pull.
6.42 idt7024s/l high-speed 4k x 16 dual-port static ram military, industrial and commercial temperature ranges 2 description the idt7024 is a high-speed 4kx 16 dual-port static ram. the idt7024 is designed to be used as a stand-alone 64k-bit dual-port ram or as a combination master/slave dual-port ram for 32-bit or more word systems. using the idt master/slave dual-port ram approach in 32-bit or wider memory system applications results in full-speed, error- free operation without the need for additional discrete logic. this device provides two independent ports with separate control, address, and i/o pins that permit independent, asynchronous access for reads or writes to any location in memory. an automatic power down feature controlled by chip enable ( ce ) permits the on-chip circuitry of each pin configurations (1,2,3) notes: 1. all v cc pins must be connected to the power supply. 2. all gnd pins must be connected to the ground supply. 3. j84-1 package body is approximately 1.15 in x 1.15 in x .17 in. f84-2 package body is approximately 1.17 in x 1.17 in x .11 in. pn100-1 package body is approximately 14mm x 14mm x 1.4mm. 4. this package code is used to reference the package diagram. 5. this text does not indicate orientation of the actual part-marking. port to enter a very low standby power mode. fabricated using idt?s cmos high-performance technology, these devices typically operate on only 750mw of power. low-power (l) versions offer battery backup data retention capability with typical power consumption of 500w from a 2v battery. the idt7024 is packaged in a ceramic 84-pin pga, an 84-pin flatpack and plcc, and a 100-pin tqfp. military grade product is manufactured in compliance with the latest revision of mil-prf-38535 qml, making it ideally suited to military temperature applications demanding the highest level of performance and reliability. 2740 drw 02 14 15 16 17 18 19 20 index 21 22 23 24 11109876543218483 33 34 35 36 37 38 39 40 41 42 43 44 45 v cc gnd i/o 8l a 7l 13 12 25 26 27 28 29 30 31 32 46 47 48 49 50 51 52 53 72 71 70 69 68 67 66 65 64 63 62 73 74 61 60 59 58 57 56 55 54 82 81 80 79 78 77 76 75 gnd busy l gnd idt7024j or f j84-1 (4) f84-2 (4) 84-pin plcc / flatpack top view (5) int l m/ s int r i/o 9l i/o 10l i/o 11l i/o 12l i/o 13l i/o 14l i/o 15l i/o 0r i/o 1r i/o 2r v cc i/o 3r i/o 4r i/o 5r i/o 6r i/o 7r i/o 8r a 6l a 5l a 4l a 3l a 2l a 1l a 0l busy r a 0r a 2r a 3r a 4r a 5r a 6r a 1r i / o 7 l i / o 6 l i / o 5 l i / o 4 l i / o 3 l i / o 2 l v c c r / w l s e m l c e l u b l l b l n / c a 1 1 l g n d i / o 1 l i / o 0 l a 1 0 l a 9 l a 8 l o e l i / o 9 r i / o 1 0 r i / o 1 1 r i / o 1 2 r i / o 1 3 r i / o 1 4 r g n d i / o 1 5 r g n d n / c a 1 1 r a 1 0 r a 9 r a 8 r a 7 r o e r r / w r s e m r c e r u b r l b r , 11/06/01 index 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 10099 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 idt7024pf pn100-1 (4) 100-pin tqfp top view (5) n/c n/c n/c n/c i/o 10l i/o 11l i/o 12l i/o 13l gnd i/o 14l i/o 15l v cc gnd i/o 0r i/o 1r i/o 2r i/o 3r v cc i/o 4r i/o 5r i/o 6r n/c n/c n/c n/c 2740 drw 03 n/c n/c n/c n/c a 5l a 4l a 3l a 2l a 1l a 0l int l gnd m/ s busy r int r a 0r n/c n/c n/c n/c busy l a 1r a 2r a 3r a 4r i / o 9 l i / o 8 l i / o 7 l i / o 6 l i / o 5 l i / o 4 l i / o 3 l i / o 2 l g n d i / o 1 l i / o 0 l o e l v c c r / w l s e m l c e l u b l l b l n / c a 1 1 l a 1 0 l a 9 l a 8 l a 7 l a 6 l i / o 7 r i / o 8 r i / o 9 r i / o 1 0 r i / o 1 1 r i / o 1 2 r i / o 1 3 r i / o 1 4 r g n d i / o 1 5 r o e r r / w r s e m r c e r u b r l b r g n d n / c a 1 1 r a 1 0 r a 9 r a 8 r a 7 r a 6 r a 5 r , 11/06/01
6.42 idt7024s/l high-speed 4k x 16 dual-port static ram military, industrial and commercial temperature ranges 3 pin names maximum operating temperature and supply voltage (1) notes: 1. all v cc pins must be connected to the power supply. 2. all gnd pins must be connected to the ground supply. 3. package body is approximately 1.12 in x 1.12 in x .16 in. 4. this package code is used to reference the package diagram. 5. this text does not indicate orientation of the actual part-marking. pin configurations (1,2,3) (con't.) notes: 1. this is the parameter t a . this is the "instant on" case temperature. 2740 drw 04 i/o 7l 63 61 60 58 55 54 51 48 46 45 66 67 69 72 75 76 79 81 82 83 125 7 8 11 10 12 14 17 20 23 26 28 29 32 31 33 35 38 41 43 idt7024g g84-3 (4) 84-pin pga top view (5) abcdefghj kl 42 59 56 49 50 40 25 27 30 36 34 37 39 84 3 4 6 9 15 13 16 18 22 24 19 21 68 71 70 77 80 ub r ce r gnd 11 10 09 08 07 06 05 04 03 02 01 64 65 62 57 53 52 47 44 73 74 78 gnd gnd r/ w r oe r lb r gnd gnd sem r n/c ub l ce l r/ w l oe l gnd sem l v cc lb l int r busy r busy l m/ s int l a 11l n/c i ndex i/o 5l i/o 4l i/o 2l i/o 0l i/o 10l i/o 8l i/o 6l i/o 3l i/o 1l i/o 11l i/o 9l i/o 13l i/o 12l i/o 15l i/o 14l i/o 0r a 9l a 10l a 8l a 7l a 5l a 6l a 4l a 3l a 2l a 0l a 1l a 0r a 2r a 1r a 5r a 3r a 6r a 4r a 9r a 7r a 8r a 10r a 11r i/o 1r i/o 2r v cc i/o 3r i/o 4r i/o 5r i/o 7r i/o 6r i/o 9r i/o 8r i/o 11r i/o 10r i/o 12r i/o 13r i/o 14r i/o 15r v cc 11/06/01 left port right port names ce l ce r chip enable r/ w l r/ w r read/write enable oe l oe r output enable a 0l - a 11 l a 0r - a 11r address i/o 0l - i/o 15l i/o 0r - i/o 15r data input/output sem l sem r semaphore enable ub l ub r upper byte select lb l lb r lower byte select int l int r interrup t flag busy l busy r busy flag m/ s master or slave select v cc power gnd ground 2740 tbl 01 grade ambient temperature gnd vcc military -55 o c to +125 o c0v5.0v + 10% commercial 0 o c to +70 o c0v5.0v + 10% industrial -40 o c to +85 o c0v5.0v + 10% 2740 tbl 02
6.42 idt7024s/l high-speed 4k x 16 dual-port static ram military, industrial and commercial temperature ranges 4 truth table i: non-contention read/write control recommended dc operating conditions truth table ii: semaphore read/write control (1) absolute maximum ratings (1) note: 1. there are eight semaphore flags written to via i/o 0 and read from all of the i/o's (i/o 0 - i/o 15 ). these eight semaphores are addressed by a 0 - a 2 . note: 1. a 0l ? a 11l a 0r ? a 11r notes: 1. stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. v term must not exceed vcc +10% for more than 25% of the cycle time or 10ns maximum, and is limited to < 20ma for the period over v term > vcc + 10% . notes: 1. v il > -1.5v for pulse width less than 10ns. 2. v term must not exceed vcc + 10%. inputs (1) outputs mode ce r/ w oe ub lb sem i/o 8-15 i/o 0-7 hxxxxhhigh-zhigh-zdeselcted: power-down x x x h h h high-z high-z both bytes deselected llxlhhdata in high-z write to up p er byte only llxhlhhigh-zdata in write to lower byte only llxllhdata in data in write to bo th byte s lhllhhdata out high-z read upper byte only lhlhlhhigh-zdata out read lower byte only lhlllhdata out data out read both bytes x x h x x x high-z high-z outputs disabled 27 40 tbl 03 inputs (1) outputs mode ce (2) r/ w oe ub lb sem i/o 8-15 i/o 0-7 hhlxx ldata out data out read semaphore flag data out xhlhhldata out data out read semaphore flag data out h xxxldata in data in write i/o 0 into semaphore flag x xhhldata in data in write i/o 0 into semaphore flag lxxlxl ____ ____ not allowed lxxxll ____ ____ not allowed 2740 tbl 04 symbol rating commercial & industrial military unit v te rm (2) terminal voltage with respect to gnd -0.5 to +7.0 -0.5 to +7.0 v t bias temperature under bias -55 to +125 -65 to +135 o c t stg storage temperature -65 to +150 -65 to +150 o c i out dc output current 50 50 ma 2740 tbl 05 symbol parameter min. typ. max. unit v cc supply voltage 4.5 5.0 5.5 v gnd ground 0 0 0 v v ih input high voltage 2.2 ____ 6.0 (2 ) v v il input low voltage -0.5 (1 ) ____ 0.8 v 2740 tbl 06
6.42 idt7024s/l high-speed 4k x 16 dual-port static ram military, industrial and commercial temperature ranges 5 dc electrical characteristics over the operating temperature and supply voltage range (v cc = 5.0v 10%) notes: 1. this parameter are determined by device characterization, but is not production tested. 2. 3dv references the interpolated capacitance when the input and output signals switch from 0v to 3v or from 3v to 0v. capacitance (t a = +25c, f = 1.0mhz) (1) notes: 1. 'x' in part number indicates power rating (s or l) 2. v cc = 5v, t a = +25c, and are not production tested. i cc dc = 120ma (typ.) 3. at f = f max , address and i/o' s are cycling at the maximum frequency read cycle of 1/t rc , and using ?ac test conditions? of input levels of gnd to 3v. 4. f = 0 means no address or control lines change. 5. port "a" may be either left or right port. port "b" is the opposite from port "a". note: 1. at vcc < 2.0v input leakages are undefined. dc electrical characteristics over the operating temperature and supply voltage range (1) (v cc = 5.0v 10%) symbol parameter conditions (2 ) max. unit c in inp ut cap acitance v in = 3dv 9 pf c out output capacitance v out = 3dv 10 pf 2740 tbl 07 symbol parameter test conditions 7024s 7024l unit min. max. min. max. |i li | input leakage current (1 ) v cc = 5.5v, v in = 0v to v cc ___ 10 ___ 5a |i lo | output leakage current ce = v ih , v out = 0v to v cc ___ 10 ___ 5a v ol output low voltage i ol = +4ma ___ 0.4 ___ 0.4 v v oh output high voltage i oh = -4ma 2.4 ___ 2.4 ___ v 2740 tbl 08 7024x15 com'l only 7024x17 com'l only 7024x20 com'l, ind & military 7024x25 com'l & military symbol parameter test condition version typ. (2) max. typ. (2) max. typ. (2) max. typ. (2 ) max. unit i cc dynamic ope rating current (both ports active) ce = v il , outputs disabled sem = v ih f = f max (3) com'l s l 170 170 310 260 170 170 310 260 160 160 290 240 155 155 265 220 ma mil & ind s l ____ ____ ____ ____ ____ ____ ____ ____ 160 160 370 320 155 155 340 280 i sb1 standby current (both ports - ttl le vel inputs) ce r = ce l = v ih sem r = sem l = v ih f = f max (3) com'l s l 20 20 60 50 20 20 60 50 20 20 60 50 16 16 60 50 ma mil & ind s l ____ ____ ____ ____ ____ ____ ____ ____ 20 20 90 70 16 16 80 65 i sb2 standby current (one port - ttl le vel inputs) ce "a" = v il and ce "b" = v ih (5) active port outp uts disab le d, f=f max (3 ) sem r = sem l = v ih com'l s l 105 105 190 160 105 105 190 160 95 95 180 150 90 90 170 140 ma mil & ind s l ____ ____ ____ ____ ____ ____ ____ ____ 95 95 240 210 90 90 215 180 i sb3 full standby current (both ports - cmos le vel inp uts) both ports ce l and ce r > v cc - 0.2v, v in > v cc - 0.2v or v in < 0.2v, f = 0 (4 ) sem r = sem l > v cc - 0.2v com'l s l 1.0 0.2 15 5 1.0 0.2 15 5 1.0 0.2 15 5 1.0 0.2 15 5 ma mil & ind s l ____ ____ ____ ____ ____ ____ ____ ____ 1.0 0.2 30 10 1.0 0.2 30 10 i sb4 full standby current (one port - cmos le vel inp uts) ce "a" < 0.2v and ce "b" > v cc - 0.2v (5) sem r = sem l > v cc - 0.2v v in > v cc - 0.2v o r v in < 0.2v active port outp uts disab le d, f = f max (3) com'l s l 100 100 170 140 100 100 170 140 90 90 155 130 85 85 145 120 ma mil & ind s l ____ ____ ____ ____ ____ ____ ____ ____ 90 90 225 200 85 85 200 170 2740 tbl 09a
6.42 idt7024s/l high-speed 4k x 16 dual-port static ram military, industrial and commercial temperature ranges 6 dc electrical characteristics over the operating temperature and supply voltage range (1) (con?t.) (v cc = 5.0v 10%) data retention characteristics over all temperature ranges (l version only) (v lc = 0.2v, v hc = v cc - 0.2v) (4) notes: 1. 'x' in part number indicates power rating (s or l) 2. v cc = 5v, t a = +25c, and are not production tested. 3. at f = f max , address and i/o' s are cycling at the maximum frequency read cycle of 1/t rc , and using ?ac test conditions?of input levels of gnd to 3v. 4. f = 0 means no address or control lines change. 5. port "a" may be either left or right port. port "b" is the opposite from port "a". notes: 1. t a = +25c, v cc = 2v, and are by device characterization but are not production tested. 2. t rc = read cycle time 3. this parameter is guaranteed but not tested. 4 . at vcc < 2.0v, input leakages are not defined. 7024x35 com'l & military 7024x55 com'l, ind & military 7024x70 military only symbol parameter test condition version typ. (2) max. typ. (2) max. typ. (2) max. uni t i cc dynamic operating current (both ports active) ce = v il , outputs disabled sem = v ih f = f max (3) com'l s l 150 150 250 210 150 150 250 210 ____ ____ ____ ____ ma mil & ind s l 150 150 300 250 150 150 300 250 140 140 300 250 i sb1 standby current (both ports - ttl level inputs) ce r = ce l = v ih sem r = sem l = v ih f = f max (3) com'l s l 13 13 60 50 13 13 60 50 ____ ____ ____ ____ ma mil & ind s l 13 13 80 65 13 13 80 65 10 10 80 65 i sb2 standby current (one port - ttl level inputs) ce "a" = v il and ce "b" = v ih (5) active port outputs disabled, f=f max (3) sem r = sem l = v ih com'l s l 85 85 155 130 95 95 155 130 ____ ____ ____ ____ ma mil & ind s l 85 85 190 160 95 95 190 160 80 80 190 160 i sb3 full standby current (both ports - cmos level inputs) both ports ce l and ce r > v cc - 0.2v, v in > v cc - 0.2v or v in < 0.2v, f = 0 (4) sem r = sem l > v cc - 0.2v com'l s l 1.0 0.2 15 5 1.0 0.2 15 5 ____ ____ ____ ____ ma mil & ind s l 1.0 0.2 30 10 1.0 0.2 30 10 1.0 0.2 30 10 i sb4 full standby current (one port - cmos level inputs) ce "a" < 0.2v and ce "b" > v cc - 0.2v (5) sem r = sem l > v cc - 0.2v v in > v cc - 0.2v or v in < 0.2v active port outputs disabled, f = f max (3) com'l s l 80 80 135 110 80 80 135 110 ____ ____ ____ ____ ma mil & ind s l 80 80 175 150 80 80 175 150 75 75 175 150 2740 tbl 09b symbol parameter test condition min. typ. (1 ) max. unit v dr v cc for data retention v cc = 2v 2.0 ___ ___ v i ccdr data retention current ce > v hc v in > v hc or < v lc mil. & ind. ___ 100 4000 a com'l. ___ 100 1500 t cd r (3 ) chip dese lect to data retention time sem > v hc 0 ___ ___ ns t r (3 ) operation recovery time t rc (2 ) ___ ___ ns 2740 tbl 10
6.42 idt7024s/l high-speed 4k x 16 dual-port static ram military, industrial and commercial temperature ranges 7 data retention waveform ac test conditions figure 2. output test load (for t lz , t hz , t wz , t ow ) *including scope and jig figure 1. ac output test load d a t a r e t e n t i o n m o d e v cc ce 2740 drw 05 4.5v t cdr t r v ih v dr v ih 4.5v v dr 2v 2740 drw 06 1250 ? 30pf 775 ? 5 v data out busy int 1250 ? 5pf* 775 ? 5v data out , input pulse levels input rise/fall times input timing reference levels output reference levels output load gnd to 3.0v 5ns 1.5v 1.5v figures 1 and 2 2740 tbl 11
6.42 idt7024s/l high-speed 4k x 16 dual-port static ram military, industrial and commercial temperature ranges 8 notes: 1. transition is measured 0mv from low or high-impedance voltage with the output test load (figure 2). 2. this parameter is guaranteed by device characterization, but is not production tested. 3. to access ram, ce = v il , ub or lb = v il , and sem =v ih . to access semaphore, ce = v ih or ub & lb = v ih , and sem =v il . 4. 'x' in part number indicates power rating (s or l). ac electrical characteristics over the operating temperature and supply voltage range (4) 7024x15 com'l only 7024x17 com'l only 7024x20 com'l, ind & military 7024x25 com'l & military unit symbol parameter min.max.min.max.min.max.min.max. read cycle t rc read cycle time 15 ____ 17 ____ 20 ____ 25 ____ ns t aa address access time ____ 15 ____ 17 ____ 20 ____ 25 ns t ace chip enable access time (3) ____ 15 ____ 17 ____ 20 ____ 25 ns t abe byte enable access time (3) ____ 15 ____ 17 ____ 20 ____ 25 ns t aoe output enable access time ____ 10 ____ 10 ____ 12 ____ 13 ns t oh output hold from address change 3 ____ 3 ____ 3 ____ 3 ____ ns t lz output low-z time (1,2) 3 ____ 3 ____ 3 ____ 3 ____ ns t hz output high-z time (1,2) ____ 10 ____ 10 ____ 12 ____ 15 ns t pu chip enable to power up time (1,2) 0 ____ 0 ____ 0 ____ 0 ____ ns t pd chip disable to power down time (1,2) ____ 15 ____ 17 ____ 20 ____ 25 ns t sop semaphore flag update pulse ( oe or sem )10 ____ 10 ____ 10 ____ 10 ____ ns t saa semaphore address access (3) ____ 15 ____ 17 ____ 20 ____ 25 ns 2740 tbl 12a 7024x35 com'l & military 7024x55 com'l, ind & military 7024x70 military only unit symbol parameter min.max.min.max.min.max. read cycle t rc read cycle time 35 ____ 55 ____ 70 ____ ns t aa address access time ____ 35 ____ 55 ____ 70 ns t ace chip enable access time (3) ____ 35 ____ 55 ____ 70 ns t abe byte enable access time (3) ____ 35 ____ 55 ____ 70 ns t aoe output enable access time ____ 20 ____ 30 ____ 35 ns t oh output hold from address change 3 ____ 3 ____ 3 ____ ns t lz output low-z time (1,2) 3 ____ 3 ____ 3 ____ ns t hz output high-z time (1,2) ____ 15 ____ 25 ____ 30 ns t pu chip enab le to power up time (1,2) 0 ____ 0 ____ 0 ____ ns t pd chip disable to power down time (1,2) ____ 35 ____ 50 ____ 50 ns t sop semaphore flag update pulse ( oe or sem )15 ____ 15 ____ 15 ____ ns t saa semaphore address access (3) ____ 35 ____ 55 ____ 70 ns 2740 tbl 12b
6.42 idt7024s/l high-speed 4k x 16 dual-port static ram military, industrial and commercial temperature ranges 9 notes: 1. timing depends on which signal is asserted last, ce , oe , lb , or ub . 2. timing depends on which signal is de-asserted first, ce , oe , lb , or ub . 3. t bdd delay is required only in cases where opposite port is completing a write operation to the same address location. for simultane ous read operations busy has no relation to valid output data. 4. start of valid data depends on which timing becomes effective last t abe , t aoe , t ace , t aa or t bdd . 5. sem = v ih . timing of power-up power-down waveform of read cycles (5) t rc r/ w ce addr t aa oe ub , lb 2740 drw 07 (4) t ace (4) t aoe (4) t abe (4) (1) t lz t oh (2) t hz (3,4) t bdd data out busy out valid data (4) ce 2740 drw 08 t pu i cc i sb t pd ,
6.42 idt7024s/l high-speed 4k x 16 dual-port static ram military, industrial and commercial temperature ranges 10 ac electrical characteristics over the operating temperature and supply voltage (5) notes: 1. transition is measured 0mv from low or high-impedance voltage with the output test load (figure 2). 2. this parameter is guaranteed by device characterization, but is not production tested. 3. to access ram, ce = v il , ub or lb = v il , sem = v ih . to access semaphore, ce = v ih or ub & lb = v ih , and sem = v il . either condition must be valid for the entire t ew time. 4. the specification for t dh must be met by the device supplying write data to the ram under all operating conditions. although t dh and t ow values will vary over voltage and temperature, the actual t dh will always be smaller than the actual t ow . 5. 'x' in part number indicates power rating (s or l). symbol parameter 7024x15 com'l only 7024x17 com'l only 7024x20 com'l, ind & military 7024x25 com'l & military unit min. max. min. max. min. max. min. max. write cycle t wc write cycle time 15 ____ 17 ____ 20 ____ 25 ____ ns t ew chip enable to end-of-write (3) 12 ____ 12 ____ 15 ____ 20 ____ ns t aw address valid to end-of-write 12 ____ 12 ____ 15 ____ 20 ____ ns t as address set-up time (3) 0 ____ 0 ____ 0 ____ 0 ____ ns t wp write pulse width 12 ____ 12 ____ 15 ____ 20 ____ ns t wr write recovery time 0 ____ 0 ____ 0 ____ 0 ____ ns t dw data valid to end-of-write 10 ____ 10 ____ 15 ____ 15 ____ ns t hz output high-z time (1,2) ____ 10 ____ 10 ____ 12 ____ 15 ns t dh data hold time (4) 0 ____ 0 ____ 0 ____ 0 ____ ns t wz write enab le to output in high-z (1,2) ____ 10 ____ 10 ____ 12 ____ 15 ns t ow output active from end-of-write (1, 2,4) 0 ____ 0 ____ 0 ____ 0 ____ ns t swrd sem flag write to read time 5 ____ 5 ____ 5 ____ 5 ____ ns t sps sem flag contention window 5 ____ 5 ____ 5 ____ 5 ____ ns 2740 tbl 13a symbol parameter 7024x35 com'l & military 7024x55 com'l, ind & military 7024x70 military only unit min. max. min. max. min. max. write cycle t wc write cycle time 35 ____ 55 ____ 70 ____ ns t ew chip enable to end-of-write (3) 30 ____ 45 ____ 50 ____ ns t aw address valid to end-of-write 30 ____ 45 ____ 50 ____ ns t as address set-up time (3) 0 ____ 0 ____ 0 ____ ns t wp write pulse width 25 ____ 40 ____ 50 ____ ns t wr write recovery time 0 ____ 0 ____ 0 ____ ns t dw data valid to end-of-write 15 ____ 30 ____ 40 ____ ns t hz output high-z time (1,2) ____ 15 ____ 25 ____ 30 ns t dh data hold time (4) 0 ____ 0 ____ 0 ____ ns t wz write enab le to output in high-z (1,2) ____ 15 ____ 25 ____ 30 ns t ow output active from end-of-write (1, 2,4) 0 ____ 0 ____ 0 ____ ns t swrd sem flag write to read time 5 ____ 5 ____ 5 ____ ns t sps sem flag contention window 5 ____ 5 ____ 5 ____ ns 2740 tbl 13b
6.42 idt7024s/l high-speed 4k x 16 dual-port static ram military, industrial and commercial temperature ranges 11 timing waveform of write cycle no. 1, r/ w controlled timing (1,5,8) timing waveform of write cycle no. 2, ce , ub , lb controlled timing (1,5) notes: 1. r/ w or ce or ub & lb = v ih during all address transitions. 2. a write occurs during the overlap (t ew or t wp ) of a ub or lb = v il and a ce = v il and a r/ w = v il for memory array writing cycle. 3. t wr is measured from the earlier of ce or r/ w (or sem or r/ w ) going high = v il to the end-of-write cycle. 4. during this period, the i/o pins are in the output state and input signals must not be applied. 5. if the ce or sem low = v il transition occurs simultaneously with or after the r/ w = v il transition, the outputs remain in the high-impedance state. 6. timing depends on which enable signal is asserted last, ce , r/ w , ub , or lb . 7. this parameter is guaranted by device characterization, but is not production tested. transition is measured 0mv steady st ate with the output test load (figure 2). 8. if oe = v il during r/ w controlled write cycle, the write pulse width must be the larger of t wp for (t wz + t dw ) to allow the i/o drivers to turn off and data to be placed on the bus for the required t dw . if oe = v ih during an r/ w controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified t wp . 9. to access ram, ce = v il , ub or lb = v il , and sem = v ih . to access semaphore, ce = v ih or ub & lb = v ih , and sem = v il . t ew must be met for either condition. r/ w t wc t hz t aw t wr t as t wp data out (2) t wz t dw t dh t ow oe address data in (6) (4) (4) (7) ub or lb 2740 drw 09 (9) ce or sem (9) (7) (3) 2740 drw 10 t wc t as t wr t dw t dh address data in r/ w t aw t ew ub or lb (3) (2) (6) ce or sem (9) (9)
6.42 idt7024s/l high-speed 4k x 16 dual-port static ram military, industrial and commercial temperature ranges 12 timing waveform of semaphore read after write timing, either side (1) notes: 1. ce = v ih or ub & lb = v ih for the duration of the above timing (both write and read cycle). 2. ?data out valid? represents all i/o's (i/o 0 -i/o 15 ) equal to the semaphore value. notes: 1. d 0r = d 0l = v il , ce r = ce l = v ih , or both ub & lb = v ih , semaphore flag is released from both sides (reads as ones from both sides) at cycle start. 2. all timing is the same for left and right ports. port ?a? may be either left or right port. port ?b? is the opposite from por t ?a?. 3. this parameter is measured from r/ w a or sem a going high to r/ w b or sem b going high. 4. if t sps is not satisfied, there is no guarantee which side will obtain the semaphore flag. timing waveform of semaphore write contention (1,3,4) sem 2740 drw 11 t aw t ew t sop i/o 0 valid address t saa r/ w t wr t oh t ace valid address data in valid data out t dw t wp t dh t as t swrd t aoe read cycle write cycle a 0 -a 2 oe valid (2) sem "a" 2740 drw 12 t sps match r/ w "a" match a 0"a" -a 2"a" side "a" (2) sem "b" r/ w "b" a 0"b" -a 2"b" side (2) "b" ,
6.42 idt7024s/l high-speed 4k x 16 dual-port static ram military, industrial and commercial temperature ranges 13 notes: 1. port-to-port delay through ram cells from writing port to reading port, refer to "timing waveform of write port-to-port read and busy (m/ s = v ih )". 2. to ensure that the earlier of the two ports wins. 3. t bdd is a calculated parameter and is the greater of 0ns, t wdd ? t wp (actual) or t ddd ? t dw (actual). 4. to ensure that the write cycle is inhibited on port 'b' during contention with port 'a'. 5. to ensure that a write cycle is completed on port 'b' after contention with port 'a'. 6. 'x' in part number indicates power rating (s or l). ac electrical characteristics over the operating temperature and supply voltage range (6) 7024x15 com'l only 7024x17 com'l only 7024x20 com'l, ind & military 7024x25 com'l & military symbol parameter min.max.min.max.min.max.min.max.unit busy timing (m/ s = v ih ) t baa busy access time from address match ____ 15 ____ 17 ____ 20 ____ 20 ns t bda busy disable time from address not match ____ 15 ____ 17 ____ 20 ____ 20 ns t bac busy access time from chip enable low ____ 15 ____ 17 ____ 20 ____ 20 ns t bdc busy disable time from chip enable high ____ 15 ____ 17 ____ 17 ____ 17 ns t aps arbitration priority set-up time (2) 5 ____ 5 ____ 5 ____ 5 ____ ns t bdd busy disable to valid data (3) ____ 18 ____ 18 ____ 30 ____ 30 ns t wh write hold after busy (5) 12 ____ 13 ____ 15 ____ 17 ____ ns busy input timing (m/ s = v ih ) t wb busy input to write (4) 0 ____ 0 ____ 0 ____ 0 ____ ns t wh write hold after busy (5) 12 ____ 13 ____ 15 ____ 17 ____ ns port-to-port delay timing t wdd write pulse to data delay (1) ____ 30 ____ 30 ____ 45 ____ 50 ns t ddd write data valid to read data delay (1) ____ 25 ____ 25 ____ 35 ____ 35 ns 2740 tbl 14a 7024x35 com'l & military 7024x55 com'l, ind & military 7024x70 military only symbol parameter min.max.min.max.min.max.unit busy timing (m/ s = v ih ) t baa busy access time from address match ____ 20 ____ 45 ____ 45 ns t bda busy disable time from address not match ____ 20 ____ 40 ____ 40 ns t bac busy access time from chip enable low ____ 20 ____ 40 ____ 40 ns t bdc busy disable time from chip enable high ____ 20 ____ 35 ____ 35 ns t aps arbitration priority set-up time (2) 5 ____ 5 ____ 5 ____ ns t bdd busy disable to valid data (3) ____ 35 ____ 40 ____ 45 ns t wh write hold after busy (5) 25 ____ 25 ____ 25 ____ ns busy input timing (m/ s = v ih ) t wb busy input to write (4) 0 ____ 0 ____ 0 ____ ns t wh write hold after busy (5) 25 ____ 25 ____ 25 ____ ns port-to-port delay timing t wdd write pulse to data delay (1) ____ 60 ____ 80 ____ 95 ns t ddd write data valid to read data delay (1) ____ 45 ____ 65 ____ 80 ns 2740 tbl 14b
6.42 idt7024s/l high-speed 4k x 16 dual-port static ram military, industrial and commercial temperature ranges 14 2740 drw 13 t dw t aps addr "a" t wc data out "b" match t wp r/ w "a" data in "a" addr "b" t dh valid (1) match busy "b" t bda valid t bdd t ddd (3) t wdd t baa timing waveform of write with port-to-port read and busy (2,4,5) (m/ s = v ih ) timing waveform of write with busy notes: 1. t wh must be met for both busy input (slave) and output (master). 2. busy is asserted on port "b" blocking r/ w "b" , until busy "b" goes high. 3. t wb is only for the 'slave' version. notes: 1. to ensure that the earlier of the two ports wins. t aps is ignored for m/ s = v il (slave). 2. ce l = ce r = v il . 3. oe = v il for the reading port. 4. if m/ s = v il (slave) then busy is an input busy "a" = v il and busy "b" = don't care, for this example. 5. all timing is the same for both left and right ports. port "a" may be either the left or right port. port "b" is the port opposite from port "a". 2740 drw 14 r/ w "a" busy "b" t wp t wb r/ w "b" t wh (1) (2) (3) ,
6.42 idt7024s/l high-speed 4k x 16 dual-port static ram military, industrial and commercial temperature ranges 15 ac electrical characteristics over the operating temperature and supply voltage range (1) waveform of busy arbitration controlled by ce timing (1) (m/ s = v ih ) waveform of busy arbitration cycle controlled by address match timing (1) (m/ s = v ih ) notes: 1. all timing is the same for left and right ports. port ?a? may be either the left or right port. port ?b? is the port opposite from ?a?. 2. if t aps is not satisfied, the busy signal will be asserted on one side or another but there is no guarantee on which side busy will be asserted. notes: 1. 'x' in part number indicates power rating (s or l). 2740 drw 15 addr "a" and "b" addresses match ce "a" ce "b" busy "b" t aps t bac t bdc (2) 2740 drw 16 addr "a" address "n" addr "b" busy "b" t aps t baa t bda (2) matching address "n" 7024x15 com'l only 7024x17 com'l only 7024x20 com'l , ind & military 7024x25 com'l & military symbol parameter min.max.min.max.min.max.min.max.unit interrupt timing t as address set-up time 0 ____ 0 ____ 0 ____ 0 ____ ns t wr write recovery time 0 ____ 0 ____ 0 ____ 0 ____ ns t ins interrupt set time ____ 15 ____ 15 ____ 20 ____ 20 ns t inr interrupt reset time ____ 15 ____ 15 ____ 20 ____ 20 ns 2740 tbl 15a 7024x35 com'l & military 7024x55 com'l, ind & military 7024x70 military only symbol parameter min.max.min.max.min.max.unit interrupt timing t as address set-up time 0 ____ 0 ____ 0 ____ ns t wr write recovery time 0 ____ 0 ____ 0 ____ ns t ins interrupt set time ____ 25 ____ 40 ____ 50 ns t inr interrupt reset time ____ 25 ____ 40 ____ 50 ns 2740 tbl 15b
6.42 idt7024s/l high-speed 4k x 16 dual-port static ram military, industrial and commercial temperature ranges 16 truth table iii ? interrupt flag (1,4) waveform of interrupt timing (1) notes: 1. assumes busy l = busy r = v ih . 2. if busy l = v il , then no change. 3. if busy r = v il , then no change. 4. int r and int l must be initialized at power-up. 2740 drw 17 addr "a" interrupt set address ce "a" r/ w "a" t as t wc t wr (3) (4) t ins (3) int "b" (2) 2740 drw 18 addr "b" interrupt clear address ce "b" oe "b" t as t rc (3) t inr (3) int "b" (2) left port right port function r/ w l ce l oe l a 11l -a 0l int l r/ w r ce r oe r a 11r -a 0r int r llxfffxxxx x l (2) se t rig ht int r flag xxx x xxll fff h (3) re se t rig ht int r flag xxx x l (3) llx ffexset left int l flag xllffe h (2) x x x x x reset left int l flag 2740 tbl 16 notes: 1. all timing is the same for left and right ports. port ?a? may be either the left or right port. port ?b? is the port opposite from ?a?. 2. see interrupt truth table iii. 3. timing depends on which enable signal ( ce or r/ w ) is asserted last. 4. timing depends on which enable signal ( ce or r/ w ) is de-asserted first.
6.42 idt7024s/l high-speed 4k x 16 dual-port static ram military, industrial and commercial temperature ranges 17 truth table iv ? address busy arbritration notes: 1. pins busy l and busy r are both outputs when the part is configured as a master. both are inputs when configured as a slave. busy x outputs on the idt7024 are push pull, not open drain outputs. on slaves, the busy asserted input internally inhibits write. 2. "l" if the inputs to the opposite port were stable prior to the address and enable inputs of this port. "h" if the inputs to the opposite port became stable after the address and enable inputs of this port. if t aps is not met, either busy l or busy r = low will result. busy l and busy r outputs cannot be low simultaneously. 3. writes to the left port are internally ignored when busy l outputs are driving low regardless of actual logic level on the pin. writes to the right port are internally ignored when busy r outputs are driving low regardless of actual logic level on the pin. notes: 1. this table denotes a sequence of events for only one of the eight semaphores on the idt7024. 2. there are eight semaphore flags written to via i/o 0 and read from all the i/o's. these eight semaphores are addressed by a0-a2. 3. ce = v ih , sem = v il , to access the semaphores. refer to the semaphore read/write control truth table. truth table v ? example of semaphore procurement sequence (1,2,3) functional description the idt7024 provides two ports with separate control, address and i/o pins that permit independent access for reads or writes to any location in memory. the idt7024 has an automatic power down feature controlled by ce . the ce controls on-chip power down circuitry that permits the respective port to go into a standby mode when not selected ( ce = v ih ). when a port is enabled, access to the entire memory array is permitted. interrupts if the user chooses the interrupt function, a memory location (mail box or message center) is assigned to each port. the left port interrupt flag ( int l ) is asserted when the right port writes to memory location ffe (hex), where a write is defined as the ce = r/ w = v il per the truth table iii. the left port clears the interrupt by access address location ffe access when ce r = oe r = v il, r/w is a "don't care". likewise, the right port interrupt flag ( int r ) is asserted when the left port writes to memory location fff (hex) and to clear the interrupt flag ( int r ), the right port must access the memory location fff. the message (16 bits) at ffe or fff is user- defined, since it is an addressable sram location. if the interrupt function inputs outputs function ce l ce r a 0l -a 11l a 0r -a 11r busy l (1) busy r (1) x x no match h h normal h x match h h normal x h match h h normal l l match (2) (2) write inhibit (3 ) 27 40 tb l 17 functions d 0 - d 15 left d 0 - d 15 right status no action 1 1 semaphore free left port writes "0" to semaphore 0 1 left port has semaphore token right port writes "0" to semaphore 0 1 no change. right side has no write access to semaphore left port writes "1" to semaphore 1 0 right port obtains semaphore token left port writes "0" to semaphore 1 0 no change. left port has no write access to semaphore right port writes "1" to semaphore 0 1 left port obtains semaphore token left port writes "1" to semaphore 1 1 semaphore free right port writes "0" to semaphore 1 0 right port has semaphore token right port writes "1" to semaphore 1 1 semaphore free left port writes "0" to semaphore 0 1 left port has semaphore token left port writes "1" to semaphore 1 1 semaphore free 2740 tbl 18
6.42 idt7024s/l high-speed 4k x 16 dual-port static ram military, industrial and commercial temperature ranges 18 figure 3. busy and chip enable routing for both width and depth expansion with idt7024 rams. is not used, address locations ffe and fff are not used as mail boxes, but as part of the random access memory. refer to truth table iii for the interrupt operation. busy logic busy logic provides a hardware indication that both ports of the ram have accessed the same location at the same time. it also allows one of the two accesses to proceed and signals the other side that the ram is ?busy?. the busy pin can then be used to stall the access until the operation on the other side is completed. if a write operation has been attempted from the side that receives a busy indication, the write signal is gated internally to prevent the write from proceeding. the use of busy logic is not required or desirable for all applications. in some cases it may be useful to logically or the busy outputs together and use any busy indication as an interrupt source to flag the event of an illegal or illogical operation. if the write inhibit function of busy logic is not desirable, the busy logic can be disabled by placing the part in slave mode with the m/ s pin. once in slave mode the busy pin operates solely as a write inhibit input pin. normal operation can be programmed by tying the busy pins high. if desired, unintended write operations can be prevented to a port by tying the busy pin for that port low. the busy outputs on the idt 7024 sram in master mode, are push- pull type outputs and do not require pull up resistors to operate. if these rams are being expanded in depth, then the busy indication for the resulting array requires the use of an external and gate. width expansion with busy logic master/slave arrays when expanding an idt7024 ram array in width while using busy logic, one master part is used to decide which side of the ram array will receive a busy indication, and to output that indication. any number of slaves to be addressed in the same address range as the master, use the busy signal as a write inhibit signal. thus on the idt7024 ram the busy pin is an output if the part is used as a master (m/ s pin = v ih ), and the busy pin is an input if the part used as a slave (m/ s pin = v il ) as shown in figure 3. if two or more master parts were used when expanding in width, a split decision could result with one master indicating busy on one side of the array and another master indicating busy on one other side of the array. this would inhibit the write operations from one port for part of a word and inhibit the write operations from the other port for the other part of the word. the busy arbitration, on a master, is based on the chip enable and address signals only. it ignores whether an access is a read or write. in a master/slave array, both address and chip enable must be valid long enough for a busy flag to be output from the master before the actual write pulse can be initiated with either the r/ w signal or the byte enables. failure to observe this timing can result in a glitched internal write inhibit signal and corrupted data in the slave. semaphores the idt7024 is an extremely fast dual-port 4k x 16 cmos static ram with an additional 8 address locations dedicated to binary semaphore flags. these flags allow either processor on the left or right side of the dual-port ram to claim a privilege over the other processor for functions defined by the system designer?s software. as an example, the semaphore can be used by one processor to inhibit the other from accessing a portion of the dual-port ram or any other shared resource. the dual-port ram features a fast access time, and both ports are completely independent of each other. this means that the activity on the left port in no way slows the access time of the right port. both ports are identical in function to standard cmos static ram and can be read from, or written to, at the same time with the only possible conflict arising from the simultaneous writing of, or a simultaneous read/write of, a non- semaphore location. semaphores are protected against such ambiguous situations and may be used by the system program to avoid any conflicts in the non-semaphore portion of the dual-port ram. these devices have an automatic power-down feature controlled by ce , the dual-port ram enable, and sem , the semaphore enable. the ce and sem pins control on-chip power down circuitry that permits the respective port to go into standby mode when not selected. this is the condition which is shown in truth table i where ce and sem = v ih . systems which can best use the idt7024 contain multiple processors or controllers and are typically very high-speed systems which are software controlled or software intensive. these systems can benefit from a performance increase offered by the idt7024's hardware semaphores, which provide a lockout mechanism without requiring complex program- ming. software handshaking between processors offers the maximum in system flexibility by permitting shared resources to be allocated in varying configurations. the idt7024 does not use its semaphore flags to control any resources through hardware, thus allowing the system designer total flexibility in system architecture. an advantage of using semaphores rather than the more common methods of hardware arbitration is that wait states are never incurred in either processor. this can prove to be a major advantage in very high-speed systems. how the semaphore flags work the semaphore logic is a set of eight latches which are independent of the dual-port ram. these latches can be used to pass a flag, or token, from one port to the other to indicate that a shared resource is in use. the semaphores provide a hardware assist for a use assignment method called ?token passing allocation.? in this method, the state of a semaphore latch is used as a token indicating that shared resource is in use. if the left processor wants to use this resource, it requests the token by setting the latch. this processor then verifies its success in setting the latch by reading 2740 drw 19 master dual port ram busy (l) busy (r) ce master dual port ram busy (l) busy (r) ce slave dual port ram busy (l) busy (r) ce slave dual port ram busy (l) busy (r) ce busy (l) busy (r) d e c o d e r ,
6.42 idt7024s/l high-speed 4k x 16 dual-port static ram military, industrial and commercial temperature ranges 19 it. if it was successful, it proceeds to assume control over the shared resource. if it was not successful in setting the latch, it determines that the right side processor has set the latch first, has the token and is using the shared resource. the left processor can then either repeatedly request that semaphore?s status or remove its request for that semaphore to perform another task and occasionally attempt again to gain control of the token via the set and test sequence. once the right side has relinquished the token, the left side should succeed in gaining control. the semaphore flags are active low. a token is requested by writing a zero into a semaphore latch and is released when the same side writes a one to that latch. the eight semaphore flags reside within the idt7024 in a separate memory space from the dual-port ram. this address space is accessed by placing a low input on the sem pin (which acts as a chip select for the semaphore flags) and using the other control pins (address, oe , and r/ w ) as they would be used in accessing a standard static ram. each of the flags has a unique address which can be accessed by either side through address pins a 0 ? a 2 . when accessing the semaphores, none of the other address pins has any effect. when writing to a semaphore, only data pin d 0 is used. if a low level is written into an unused semaphore location, that flag will be set to a zero on that side and a one on the other side (see truth table iii). that semaphore can now only be modified by the side showing the zero. when a one is written into the same location from the same side, the flag will be set to a one for both sides (unless a semaphore request from the other side is pending) and then can be written to by both sides. the fact that the side which is able to write a zero into a semaphore subsequently locks out writes from the other side is what makes semaphore flags useful in interprocessor communications. (a thorough discussion on the use of this feature follows shortly.) a zero written into the same location from the other side will be stored in the semaphore request latch for that side until the semaphore is freed by the first side. when a semaphore flag is read, its value is spread into all data bits so that a flag that is a one reads as a one in all data bits and a flag containing a zero reads as all zeros. the read value is latched into one side?s output register when that side's semaphore select ( sem ) and output enable ( oe ) signals go active. this serves to disallow the semaphore from changing state in the middle of a read cycle due to a write cycle from the other side. because of this latch, a repeated read of a semaphore in a test loop must cause either signal ( sem or oe ) to go inactive or the output will never change. a sequence write/read must be used by the semaphore in order to guarantee that no system level contention will occur. a processor requests access to shared resources by attempting to write a zero into a semaphore location. if the semaphore is already in use, the semaphore request latch will contain a zero, yet the semaphore flag will appear as one, a fact which the processor will verify by the subsequent read (see truth table iii). as an example, assume a processor writes a zero to the left port at a free semaphore location. on a subsequent read, the processor will verify that it has written successfully to that location and will assume control over the resource in question. meanwhile, if a processor on the right side attempts to write a zero to the same semaphore flag it will fail, as will be verified by the fact that a one will be read from that semaphore on the right side during subsequent read. had a sequence of read/write been used instead, system contention problems could have occurred during the gap between the read and write cycles. it is important to note that a failed semaphore request must be followed by either repeated reads or by writing a one into the same location. the reason for this is easily understood by looking at the simple logic diagram of the semaphore flag in figure 4. two semaphore request latches feed into a semaphore flag. whichever latch is first to present a zero to the semaphore flag will force its side of the semaphore flag low and the other side high. this condition will continue until a one is written to the same semaphore request latch. should the other side?s semaphore request latch have been written to a zero in the meantime, the semaphore flag will flip over to the other side as soon as a one is written into the first side?s request latch. the second side?s flag will now stay low until its semaphore request latch is written to a one. from this it is easy to understand that, if a semaphore is requested and the processor which requested it no longer needs the resource, the entire system can hang up until a one is written into that semaphore request latch. the critical case of semaphore timing is when both sides request a single token by attempting to write a zero into it at the same time. the semaphore logic is specially designed to resolve this problem. if simultaneous requests are made, the logic guarantees that only one side receives the token. if one side is earlier than the other in making the request, the first side to make the request will receive the token. if both requests arrive at the same time, the assignment will be arbitrarily made to one port or the other. one caution that should be noted when using semaphores is that semaphores alone do not guarantee that access to a resource is secure. as with any powerful programming technique, if semaphores are misused or misinterpreted, a software error can easily happen. initialization of the semaphores is not automatic and must be handled via the initialization program at power-up. since any semaphore request flag which contains a zero must be reset to a one, all semaphores on both sides should have a one written into them at initialization from both sides to assure that they will be free when needed. using semaphores?some examples perhaps the simplest application of semaphores is their application as resource markers for the idt7024?s dual-port ram. say the 4k x 16 ram was to be divided into two 2k x 16 blocks which were to be dedicated at any one time to servicing either the left or right port. semaphore 0 could be used to indicate the side which would control the lower section of memory, and semaphore 1 could be defined as the indicator for the upper section of memory. to take a resource, in this example the lower 2k of dual-port ram, the processor on the left port could write and then read a zero in to semaphore 0. if this task were successfully completed (a zero was read back rather than a one), the left processor would assume control of the lower 2k. meanwhile the right processor was attempting to gain control of the resource after the left processor, it would read back a one in response to the zero it had attempted to write into semaphore 0. at this point, the software could choose to try and gain control of the second 2k section by writing, then reading a zero into semaphore 1. if it succeeded in gaining control, it would lock out the left side. once the left side was finished with its task, it would write a one to semaphore 0 and may then try to gain access to semaphore 1. if semaphore 1 was still occupied by the right side, the left side could undo its semaphore request and perform other tasks until it was able to write, then
6.42 idt7024s/l high-speed 4k x 16 dual-port static ram military, industrial and commercial temperature ranges 20 read a zero into semaphore 1. if the right processor performs a similar task with semaphore 0, this protocol would allow the two processors to swap 2k blocks of dual-port ram with each other. the blocks do not have to be any particular size and can even be variable, depending upon the complexity of the software using the semaphore flags. all eight semaphores could be used to divide the dual- port ram or other shared resources into eight parts. semaphores can even be assigned different meanings on different sides rather than being given a common meaning as was shown in the example above. semaphores are a useful form of arbitration in systems like disk interfaces where the cpu must be locked out of a section of memory during a transfer and the i/o device cannot tolerate any wait states. with the use of semaphores, once the two devices has determined which memory area was ?off-limits? to the cpu, both the cpu and the i/o devices could access their assigned portions of memory continuously without any wait states. d 2740 drw 20 0 d q write d 0 d q write semaphore request flip flop semaphore request flip flop l p o r t rport semaphore read semaphore read , figure 4. idt7024 semaphore logic semaphores are also useful in applications where no memory ?wait? state is available on one or both sides. once a semaphore handshake has been performed, both processors can access their assigned ram segments at full speed. another application is in the area of complex data structures. in this case, block arbitration is very important. for this application one processor may be responsible for building and updating a data structure. the other processor then reads and interprets that data structure. if the interpreting processor reads an incomplete data structure, a major error condition may exist. therefore, some sort of arbitration must be used between the two different processors. the building processor arbitrates for the block, locks it and then is able to go in and update the data structure. when the update is completed, the data structure block is released. this allows the interpreting processor to come back and read the complete data structure, thereby guaranteeing a consistent data structure.
6.42 idt7024s/l high-speed 4k x 16 dual-port static ram military, industrial and commercial temperature ranges 21 ordering information note: 1. industrial temperature range is available on selected plcc packages in standard power. for other speeds, packages and powers c ontact your sales office. 2. green parts available. for specific speeds, packages and powers contact your local sales office. 2740 drw 21 a power 999 speed a package a process/ temperature range blank i (1) b commercial (0 cto+70 c) industrial (-40 cto+85 c) military (-55 c to +125 c) compliant to mil-prf-38535 qml pf g j f 100-pin tqfp (pn100-1) 84-pin pga (g84-3) 84-pin plcc (j84-1) 84-pin flatpack (f84-2) 15 17 20 25 35 55 70 commercial only commercial only commercial, industrial & military commercial & military commercial & military commercial, industrial & military military only s l standard power low power xxxxx device type 64k (4k x 16) dual-port ram 7024 speed in nanoseconds a g (2) green datasheet document history 1/13/99: initiated datasheet document history converted to new format cosmetic and typographical corrections pages 2 and 3 added additional notes to pin configurations 6/4/99: changed drawing format page 1 corrected dsc number 4/4/00: replaced idt logo page 6 corrected typo in data retention chart changed 500mv to 0mv in notes 5/19/00: page 3 clarified t a parameter page 4 increased storage temperature parameter pages 5 and 6 dc electrical parameters?changed wording from "open" to "disabled" datasheet document history continued on page 22
6.42 idt7024s/l high-speed 4k x 16 dual-port static ram military, industrial and commercial temperature ranges 22 corporate headquarters for sales: for tech support: 6024 silver creek valley road 800-345-7015 or 408-284-8200 408-284-2794 san jose, ca 95138 fax: 408-824-2775 dualporthelp@idt.com www.idt.com the idt logo is a registered trademark of integrated device technology, inc. datasheet document history (continued) 9/12/01: page 2 & 3 added date revision for pin configurations page 5 added industrial temp to the column heading for 20ns to dc electrical characteristics pages 8,10,13&15 added industrial temp to the column headings for 20ns to ac electrical characteristics pages 3,5,6,8,10,13&15 removed industrial temp note from all tables footnotes page 21 added industrial to 20ns ordering information 07/25/05: page 1 added green availability to features page 21 added green indicator to ordering information page 1 & 21 replaced old idt ? logo with the new idt tm logo page 21 updated address and phone contact information 10/29/08: page 21 removed "idt" from orderable part number

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